When an external information signal is input to a data processor, the external information signal is generally provided at a frequency which is asynchronous to an operating frequency of the data processor. Therefore, before the information signal may be processed and manipulated by internal circuitry within the data processing system, the information signal must be synchronized with the operating frequency of the data processor. Typically, to synchronize the external information signal with the operating frequency of the data processor, the external information signal and a clock signal reflecting the operating frequency of the data processing system are input to a synchronization circuit located within the data processor. The synchronization circuit is generally comprised of a differential amplifier and a bias generator. The external information signal and the clock signal respectively provide a first and a second input of the differential amplifier. The bias generator then provides a bias voltage to a third input of the differential amplifier to enable the differential amplifier to provide a synchronized information signal to remaining circuitry in the data processing system.
To quickly execute the synchronization process and, therefore, add only a slight propagation delay to the input information signal, a fast-switching input synchronizer is sometimes used to synchronize the input information signal to the data processing system. The fast-switching input synchronizer requires a significant amount of current, however, and significantly adds to the power requirements of the entire data processor. However, power consumption in all data processors must be continually minimized to enhance performance in all environments. For example, if a battery provides power for a data processor system, the power consumption of the system must be minimal to enable a user of the system to operate the system for a reasonable amount of time before replacing or recharging the battery. For that reason, the power consumption of each component of the data processing system must be minimized.
Typically, to lower the power consumption of each component of the data processing system, the system may be placed in a low power stop mode of operation. During the low power stop mode of operation, one or a minimum number of clock signals remain functional so the system may become operational when an appropriate external information signal is received. However, the remainder of the clock signals within the data processing system are turned off and, therefore, the components of the data processing system associated with the remainder of the clock signals do not function. Consequently, the associated components do not consume power.
To receive the external information signal from a user of the data processing system, a plurality of input synchronizers, each corresponding to one of a plurality of input pins of the system, must be constantly enabled. Upon receipt of the external information signal, the bias generator must enable the differential amplifier to provide the appropriate signal to internal circuitry within the data processing system. Because the bias generator must be enabled during operation of the data processing system, a significant amount of power is typically consumed. In particular, fast-switching input synchronizers which are often needed to maximize performance of the data processing system use bias generators which must be enabled, and therefore, consume a significant amount of power.
Because input synchronizers consume an excessive amount of power, some designers of data processing systems eliminate the bias generator from the synchronizer circuitry. Therefore, the input synchronizer requires a longer amount of time to provide a signal to internal circuitry with the data processing system. A delay is subsequently introduced and the internal circuitry of the system must wait to receive an external information signal. For these reasons, a designer of a data processing system must generally compromise either the most efficient operation of the data processing system or the speed with which external information signals are processed by the system.
Therefore, a need exists for an internal synchronizer circuit in a data processing system which quickly provides an external information signal to internal circuitry within the system while consuming a minimum amount of power. The data processing system might then be used in a wider variety of environments while maintaining a high level of performance.